Semiconductor device and manufacturing method

ABSTRACT

A semiconductor device has a Si substrate, a gate insulating film over the Si substrate, a gate electrode over the gate insulating film, a source region and a drain region in the Si substrate, wherein each of the source region and the drain region includes a first Si layer including Ge, an interlayer over the first Si layer, and a second Si layer including Ge over the interlayer, wherein the interlayer is composed of Si or Si including Ge, and a Ge concentration of the interlayer is less than a Ge concentration of the first Si layer and a Ge concentration of the second Si layer.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is based upon and claims the benefit of priority fromthe prior Japanese Patent Application No. 2007-28345, filed on Feb. 7,2007, the entire content of which is incorporated herein by reference.

TECHNICAL FIELD

The present invention relates to a semiconductor device and amanufacturing method thereof and more specifically to a semiconductordevice comprising a MOS transistor having a stress applying mechanismand a manufacturing method thereof.

BACKGROUND

Improvement in fine structures has been continuing for improvingintegration density and also improving processing speed of a siliconsemiconductor integrated circuit. Gate length of the MOS transistor hasbeen shortened in combination with further improvement in finestructure. When the gate length is 65 nm or less, expectation forimprovement of performance with a fine structure has been accompanied bylimitations.

A strain transistor for improving mobility of carriers by creating astrain is a technology for realizing improvement in performance of theMOS transistor. Strain is generated by impressing stress to a channelregion of a MOS transistor. ON-current is improved by raising mobilityof electrons and holes.

An n-channel MOS transistor can improve mobility of electrons when atensile stress is impressed to the channel region thereof. A p-channelMOS transistor can improve mobility of holes when a compressed stress isimpressed to the channel region thereof.

In the case of a PMOS transistor, when a source/drain region is formedwith a silicon-germanium (SiGe) mixed crystal having a lattice constantlarger than that of the Si substrate, a compressed stress is applied tothe Si crystal of the channel region and thereby mobility of holeincreases.

In the case of NMOS transistor, when the source/drain region is formedwith a silicon-carbon (SiC) mixed crystal having the lattice constantsmaller than that of the Si substrate, a tensile stress is applied tothe Si crystal of the channel region and thereby mobility of electronsincreases.

When the Si—Ge crystal is formed with the epitaxial growth on the Sisubstrate, thickness of the epitaxial layer which can be grown withoutmisfit dislocation is limited to the thickness called the critical filmthickness.

SUMMARY

According to an aspect of the invention, a semiconductor device has a Sisubstrate, a gate insulating film over the Si substrate, a gateelectrode over the gate insulating film, a source region and a drainregion in the Si substrate, wherein each of the source region and thedrain region includes a first Si layer including Ge, a interlayer overthe first Si layer, and a second Si layer including Ge over theinterlayer, wherein the interlayer is composed of Si or Si including Ge,and a Ge concentration of the interlayer is lower than a Geconcentration of the first Si layer and a Ge concentration of the secondSi layer.

It is also possible to form the device of the current invention bysubstituting SiC for SiGe.

BRIEF DESCRIPTION OF THE DRAWINGS

FIGS. 1A to 1C are schematic cross-sectional views showing structures ofsamples SA, SB, and SC, while FIGS. 1D to 1F are electron microscopeimages of Atomic Force Microscope (AFM) at the surface of the samplesSA, SB, and SC.

FIGS. 2A and 2B are cross-sectional views of the semiconductor device ofthe first embodiment and a modified example thereof.

FIGS. 3A to 3F are schematic cross-sectional views showing the steps inthe manufacturing method of the semiconductor device shown in FIG. 2.

FIG. 4 is a schematic plan view of the CMOS device of the secondembodiment.

FIG. 5 is a graph showing change in the critical film thickness.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT

In order to manufacture a strain PMOS transistor, a recess is formed byetching the region schemed as the source/drain area of the Si substrateand a SiGe film is formed by epitaxial growth on the Si crystal of therecess. The SiGe film may include other elements for example C. In viewof avoiding dislocation, the SiGe film which is thinner than thecritical film thickness determined by the Ge composition is grown. Whenthe SiGe film is grown exceeding a predetermined film thickness,dislocation is generated in the SiGe film. The maximum thickness notgenerating dislocation is called the critical film thickness. Whendislocation is generated, a stress is released and it becomes impossibleto effectively apply strain to the channel. Therefore, film thickness isset thinner than the critical film thickness or the Ge composition islowered. In any case, a stress to be applied to the channel region isreduced if the critical film thickness requirements are not met.

Critical film thickness in the hetero-epitaxial growth will be explainedhereunder. Here, it is assumed that a SiGe mixed crystal is formed byepitaxial growth on the surface of a Si substrate. When Ge composition xin the SiGe mixed crystal expressed by Si_(1-x)Ge_(x) is higher thanabout 0.2, the further the thickness of the epitaxial layer increases,the more strain energy to be accumulated increases also and dislocationis generated at a certain thickness. This dislocation is called themisfit dislocation. Critical film thickness also depends on film formingtemperature.

FIG. 5 is a graph showing the relationship of the critical filmthickness for Ge concentration. The vertical axis shows the criticalfilm thickness, while the horizontal axis shows the Ge concentration.When epitaxial growth occurs at the temperature (a), the more the Geconcentration increases, the larger the lattice constant of SiGe becomesand thereby the critical film thickness becomes small. When temperature(a) is set to a lower value (b), the critical film thickness increases.In the case where the SiGe mixed crystal in the lattice constantdifferent from that of Si is grown without generation of misfitdislocation on the Si crystal, the thickness thereof is restricted bythe critical film thickness.

As explained above, when the Ge concentration becomes greater, thecritical film thickness of SiGe becomes small and therefore dislocationis easily generated within SiGe. When dislocation is generated withinSiGe, strain accumulated within SiGe is also released and therefore astress applied to Si also becomes small.

When it is requested to apply, for example, a compressed stress to thechannel of MOS transistor, the compressed stress is applied from thesides of the source and drain to the channel by first forming a recessby etching the Si substrate at the part where the source/drain region isformed, and next, the SiGe mixed crystal having the lattice constantlarger than that of Si is formed by epitaxial growth within the recess.The larger the compressed stress is, the further the mobility of holesbecomes. According to the present invention, it is possible to form theSiGe layer with a thickness exceeding the critical film thickness underthe condition that generation of dislocation is controlled, and therebythe compressed stress is applied more effectively. Specifically, theinventors of the present invention have experimented with the influenceon misfit dislocation under the condition that the layer having largerdifference of lattice constant is divided with the layer having smallerlattice constant in the thickness direction.

FIGS. 1A, 1B, and 1C show three kinds of cross-sectional structures ofsamples. FIG. 1A shows a first sample SA. A Si_(0.76)Ge_(0.24) layer 22is epitaxially grown in the thickness of 25 nm on the surface of the Sisubstrate. A Si_(0.76)Ge_(0.24) means that the SiGe mixed Crystalincludes 76% Si and 24% Ge in atomic %. FIG. 1B shows a second sampleSB. A Si_(0.76)Ge_(0.24) layer 22 is epitaxially grown in the thicknessof 25 nm on the Si substrate 21, a Si layer 23 is epitaxially grownthereon in the thickness of 3 nm, and moreover a Si_(0.76)Ge_(0.24)layer 24 is epitaxially grown in the thickness of 25 nm. FIG. 1C shows athird sample SC. A Si_(0.76)Ge_(0.24) layer 25 is epitaxially grown inthe thickness of 50 nm on the front surface of the Si substrate 21. Thetotal thickness of the SiGe layer is 50 nm in the second sample SB andthe third sample SC.

The epitaxial growth has been executed under the substrate temperaturerange from 500° C. to 700° C. using the mixed gas of SiH₄, GeH₄, HCl,and H₂. The Ge composition has been controlled depending on a partialpressure ratio of the mixed gas.

FIGS. 1D, 1E, and 1F show images of AFM at the surfaces of the samplesSA, SB, and SC. AFM of the sample SA of FIG. 1D shows a flat frontsurface. Meanwhile, AFM of the sample SC of FIG. 1F shows generation ofcross-hatched stepped portion. The stepped portion corresponds to adislocation portion. Here, it is assumed that strain energy accumulatedin the SiGe layer 25 becomes too large to be held within the epitaxiallayer 25 and thereby misfit dislocation has been generated. In regard tothe sample SA of FIG. 1D, it is assumed that the stepped portion isnever generated, thickness of the epitaxial layer 22 is equal to or lessthan the critical film thickness, and misfit is not easily generated. Asexplained above, generation of dislocation may be determined with AFM.

AFM of the sample SB of FIG. 1E shows limited generation of steppedportions. The density thereof is extraordinarily smaller than that ofthe stepped portions of the sample SC of FIG. 1F. A sum of thickness ofthe SiGe layers 22, 24 is 50 nm which is identical to the thickness ofSiGe layer 25 of the sample SC, but generation of dislocation isreduced. According to these experiments, it has been determined thatwhen a thinner Si layer is inserted into the intermediate location inthe thickness direction of a SiGe layer with a total thickness of 50 nm,generation of dislocation is reduced.

Adjustment of thickness or the like in each layer results in anepitaxial layer with less dislocation. A similar effect can also beexpected by inserting a layer having small difference of latticeconstant from the substrate into the intermediate location in thethickness direction of the layer having a large difference of latticeconstant. Namely, it is possible to use SiGe having small Ge compositionin place of the Si layer.

Other materials may be used as the epitaxial layer having a largedifference of lattice constant from the substrate. A mixed crystalhaving a lattice constant smaller than that of Si may be substituted forthe SiGe mixed crystal having a lattice constant larger than that of Si.For example, it is also possible to attain a similar effect by using theSiC mixed crystal having a diamond structure like Si and a latticeconstant smaller than that of Si and then increasing the Si layer or theSiC mixed crystal having small C composition into the intermediatelocation in the thickness direction. With the SiC mixed crystal having asmall lattice constant, a larger tensile stress can be applied. A largetensile stress can be applied to the channel of NMOS transistor byarranging the SiC laminated layer having the sum of thickness exceedingthe critical film thickness to the source/drain of NMOS transistor. Thelarger tensile stress contributes to improving mobility of electrons.

A layer having a smaller lattice constant for the substrate inserted tothe intermediate location may not be limited only to a single layer. Itis possible to attain a larger total sum of thickness in the epitaxiallayer having a large difference of lattice constant from the substrate.

The B-doped type p SiGe/Si/SiGe epitaxial layer has also been formed byepitaxial growth by adding B₂H₆ as the impurity source gas. Boronconcentration is set from 1E19 cm⁻³ to 1E21 cm⁻³, but electricactivation coefficient of boron taken into the epitaxial layer hasalmost reached 100% even in the case of high concentration doping ofabout 1E20 cm⁻³.

Various epitaxial growth conditions may be introduced. For example,Si₂H₂, SiH₂Cl₂ or the like may be used as the source gas of Si, whileGe₂H₆ or the like may be used as the source gas of Ge. In the case oflaminated layers of SiC/Si or SiC/SiC, the epitaxial growth of SiC maybe conducted under the substrate temperature range from 600° C. to 900°C. using SiH₃ as the C source. As the type n impurity, PH₃, AsH₃ or thelike may be used.

FIG. 2A is a cross-sectional diagram showing the semiconductor device ofthe first embodiment on the basis of experimental results detailedabove. An element isolating region 2 is formed in the Si substrate 1with Shallow Trench Isolation (STI) method and type n impurity ision-implanted to an active region defined with the element isolatingregion 2 in order to form a type n well NW. For example, a gateinsulating film 3 formed with a silicon oxide film in the thickness of 1nm to 2 nm and a p-type impurity-doped such as boron-doped polysiliconfilm 4 are laminated on the front surface of active region and then thislaminated layer is patterned to constitute a gate electrode. On theside-wall of the gate electrodes 4, 3, insulating side-wall spacers SWare formed with the laminated layers of silicon oxide film 6 and siliconnitride film 7. The structure explained above allows varioussubstitutions, variations and modifications. For example, the gateinsulating film 3 may also be formed of laminated layers of the siliconnitride oxide film, silicon oxide film and a film of material havinghigher specific dielectric coefficient. The side-wall spacer SW may beformed of a single layer or of laminated layers of the other materials.

The recess 11 is formed by etching of the Si substrate in both sides ofthe insulating side-wall spacer SW and the first SiGe layer 12 a withhigher Ge composition, the second SiGe layer 12 b with lower Gecomposition, and the third SiGe layer 12 c with higher Ge compositionare epitaxially formed within the recess. When composition of the firstSiGe layer 12 a is expressed as Si_(1-x)Ge_(x), while composition of thesecond SiGe layer as Si_(1-y)Ge_(y), and composition of the third SiGelayer as Si_(1-z)Ge_(z), x and z are set to satisfy the relationship of0.2≦∀(x,z)≦0.4 and y is also set to satisfy the relationship of0≦y<∀(x,z). ∀(x,z) means both x and z. The first to third SiGe epitaxiallayers are all designated as 12. Boron is doped in to concentration of1E19 cm⁻³ to 1E21 cm⁻³ to the SiGe epitaxial laminated layer 12.

Generation of dislocation may be reduced even if the total sum of thefirst and the third SiGe layer becomes large with epitaxial growth ofthe first and third SiGe layer with higher Ge composition in both sidesof the second SiGe layer with lower Ge composition.

It is also possible to form an n-channel MOS transistor by inverting allconductivity types of impurity, substituting the SiGe layer with SiClayer and then selecting C composition in place of Ge composition.Silicon-carbon mixed crystal (SiC) also may include other elements.

On the occasion of using the SiC layer, when composition of the firstSiC layer is expressed as Si_(i-x)C_(x), composition of the second SiClayer as Si_(1-y)C_(y), composition of the third SiC as Si_(1-z)C_(z), xand z are set to satisfy the relationship of 0.01≦∀(x,z)≦0.02 and y isalso set to satisfy the relationship of 0≦y<∀(x,z). Here, ∀(x,z) meansboth x and z.

FIG. 2B is a cross-sectional diagram showing a modified example of thefirst embodiment. The SiGe epitaxial laminated layer 12 embedded in therecess is formed thinner than the critical film thickness and includesthe SiGe layers 12 a, 12 c, . . . , 12 y having higher Ge compositionand a plurality of SiGe layers 12 b, 12 d, . . . , 12 x inserted todivide these above layers and to have lower Ge composition. The SiGelayers 12 are all formed as the epitaxially grown layers. Other pointsare identical to the first embodiment.

FIGS. 3A to 3F are cross-sectional diagrams showing the principal stepsin the manufacturing method for manufacturing the semiconductor deviceshown in FIG. 2A.

As shown in FIG. 3A, the element isolating region 2 is formed in the Sisubstrate with the STI method to define a plurality of active regions.An n-type impurity is ion-implanted to the active region for PMOStransistor to form an n-type well NW. A p-type impurity is ion-implantedto the active region for NMOS transistor to form a p-type well. The Sisurface in the active region is exposed and a silicon oxide film isgrown in the thickness of 1 nm to 2 nm with the thermal oxidation. Here,it is also possible to introduce nitrogen from the surface to form asilicon nitride oxide film. The silicon oxide film may also be laminatedwith another insulating film(s) having higher dielectric coefficient bythe Chemical Vapor Deposition (CVD) method or the like. A gateinsulating film 3 can be formed as explained above. A polysilicon film 4is deposited over the gate insulating film 3 with the CVD method.Alternative to this process, an amorphous silicon film may be formedover the gate insulating film 3, followed by heat treatment forcrystallization to form a polysilicon film. The p-type impurity ision-implanted into the polysilicon film 4 of the PMOS transistor. Aphotoresist mask PR is formed over the polysilicon film 4, thepolysilicon film 4 is etched and the gate electrode is then patterned.Thereafter, the photoresist mask PR is removed.

As shown in FIG. 3B, the silicon oxide film 6 and the silicon nitridefilm 7 are deposited over the Si substrate with the CVD method and thenthe side-wall spacer SW on the gate electrode side-wall is left byconducting the anisotropic etching with the reactive ion etching method.Material and number of layers of side-wall spacer may be changedvariously.

As shown in FIG. 3C, the Si substrate in both sides of the side-wallspacer SW is etched with the reactive etching method using HBr as theetching gas with such side-wall spacer SW used as the mask in view offorming the recess 11.

As shown in FIG. 3D, the first SiGe layer 12 a is epitaxially grown. TheSiGe mixed crystal with Ge composition of 0.2 to 0.4 is epitaxiallygrown to a thickness less than the critical film thickness, for example,20 nm in a substrate temperature ranging from 500° C. to 700° C. usingthe mixed gas of SiH₄, GeH₄, HCl, H₂ and B₂H₆.

As shown in FIG. 3E, the supply rate of GeH₄ gas is reduced and thesecond SiGe layer 12 b with Ge composition of 0 to 0.2 is epitaxiallygrown over the first SiGe layer 12 a. For example, the Si layer is grownin the thickness of 3 nm.

As shown in FIG. 3F, the supply rate of GeH₄ gas is increased again andthe third SiGe layer 12 c with Ge composition of 0.2 to 0.4 isepitaxially grown over the second SiGe layer 12 b. Here, it is alsopossible to keep the flow rate of mixed gas to a constant rate byadjusting supply rate of H₂ as required.

As explained above, the first, second, and third SiGe layers 12 a, 12 b,12 c are embedded in the recess. A sum of thickness of the first andthird SiGe epitaxial layers 12 a, 12 c with Ge composition of 0.2 to 0.4is larger than the critical film thickness. Generation of dislocationcan be controlled even when the SiGe epitaxial layer is grown to athickness as the sum of thicknesses exceeding the critical filmthickness by providing the second SiGe epitaxial layer with lower Gecomposition at the intermediate portion. Since the SiGe epitaxial layerhaving the total thickness larger than the critical film thickness canbe allocated, a larger compressed stress may be applied to the channelregion of the PMOS transistor. Thereby, mobility of holes may beimproved with a large compressed stress.

Here, it is also allowed that the SiGe epitaxial layer with lower Gecomposition and the SiGe epitaxial layer with higher Ge composition arefurther formed over the laminated layers of three layers. Number oflayers of the laminated layer may be selected as required.

FIG. 4 is a plan view showing a part of a CMOS transistor device of thesecond embodiment. An active region for NMOS transistor and an activeregion for PMOS transistor are formed. A gate electrode G is formedtraversing the NMOS transistor region and the PMOS transistor region.The Si substrate in both sides of the gate electrode is etched in atleast one of the NMOS transistor region and PMOS transistor region inview of forming the recess. The SiGe laminated layer is epitaxiallyformed within the recess in the case of the PMOS transistor, while theSiC laminated layer is formed in the case of the NMOS transistor. In thecase of the SiGe laminated layer for embedding the recess formsource/drain of the PMOS transistor, this layer is identical to thelaminated layer of the SiGe laminated layer explained with reference toFIGS. 2A, 2B, and 3F. In the case of the SiC laminated layer embeddingthe recess for source/drain of the NMOS transistor, conductivity type ofimpurity explained with reference to FIGS. 2A, 2B, and 3F is inverted,SiC is substituted for SiGe, and C composition is substituted for Gecomposition.

Here, a film TF for applying a tensile stress such as a silicon nitridefilm may be deposited by the thermal CVD method covering the NMOStransistor and a film CF for applying a compressed stress such as asilicon nitride film may also be deposited by the plasma CVD methodcovering the PMOS transistor. In this case, it is preferable that theboundary of both stress films is formed nearer to the PMOS transistorthan the NMOS transistor. The reason is that the tensile stress canimprove mobility in both NMOS transistor and PMOS transistor in regardto the stress in the channel width direction. Here, it is also possiblethat the SiGe epitaxial laminated layer is embedded in the source/drainof the PMOS transistor to form the film TF for applying the tensilestress to the entire surface of the substrate.

The present invention is not limited only to these embodiments. Forexample, Moreover, various modifications, additions, improvements,substitutions and combinations of such contents may also be apparent forthose who are skilled in this art.

1. A semiconductor device comprising: a Si substrate; a gate insulatingfilm over the Si substrate; a gate electrode over the gate insulatingfilm; a source region and a drain region in the Si substrate; whereineach of the source region and the drain region includes a first Si layerincluding Ge, an interlayer over the first Si layer, and a second Silayer including Ge over the interlayer, wherein the interlayer iscomposed of Si or Si including Ge, and a Ge concentration of theinterlayer is less than a Ge concentration of the first Si layer and aGe concentration of the second Si layer.
 2. The semiconductor deviceaccording to claim 1, wherein the first Si layer is lattice matching tothe Si substrate, the interlayer is lattice matching to the first Silayer, the second Si layer is lattice matching to the interlayer.
 3. Thesemiconductor device according to claim 1 further comprising a recess inthe Si substrate, wherein the first Si layer, the interlayer, and thesecond Si layer are formed in the recess.
 4. The semiconductor deviceaccording to claim 1, wherein the Ge concentration of the first Si layerand the Ge concentration of the second Si layer is in the range from 20%to 40% in atomic %.
 5. The semiconductor device according to claim 1,wherein each of the source region and the drain region includes B asp-type impurity, and a concentration of B is in the range from 1×10¹⁹cm⁻³ to 1×10²¹ cm⁻³.
 6. A semiconductor device comprising: a Sisubstrate; a gate insulating film over the Si substrate; a gateelectrode over the gate insulating film; a source region and a drainregion in the Si substrate; wherein the each of the source region andthe drain region includes a first Si layer including C over the Sisubstrate, an interlayer over the first Si layer, and a second Si layerincluding C over the interlayer, wherein the interlayer is composed ofSi or Si including C, and a C concentration of the interlayer is lessthan a C concentration of the first Si layer and a C concentration ofthe second Si layer.
 7. The semiconductor device according to claim 6,wherein the first Si layer is lattice matching to the Si substrate, theinterlayer is lattice matching to the first Si layer, the second Silayer is lattice matching to the interlayer.
 8. The semiconductor deviceaccording to claim 6, an interface between the first Si layer and the Sisubstrate is lower than the surface of the Si substrate.
 9. Thesemiconductor device according to claim 6, wherein the C concentrationof the first Si layer and the C concentration of the second Si layer isin the range from 1% to 2% in atomic %.
 10. The semiconductor deviceaccording to claim 6, wherein each the source and the drain regionincludes P or As as n-type impurity, and the concentration of P or As isin the range from 1×10¹⁹ cm⁻³ to 1×10²¹ cm⁻³.
 11. A method ofmanufacturing a semiconductor device comprising: forming a gateinsulating film and a gate electrode over a Si substrate; forming arecess in the Si substrate at both sides of the gate electrode; forminga first Si layer including Ge in the recess; forming an interlayer overthe first Si layer; forming a second Si layer including Ge over theinterlayer; wherein the interlayer is composed of Si or Si including Ge,and a Ge concentration of the interlayer is less than a Ge concentrationof the first Si layer and a Ge concentration of the second Si layer. 12.The method of manufacturing the semiconductor device according to claim11, wherein the first Si layer is formed by epitaxial growth, theinterlayer is formed by epitaxial growth, and the second Si layer isformed by epitaxial growth.
 13. The method of manufacturing thesemiconductor device according to claim 11, wherein a thickness of eachof the first Si layer, and the second Si layer is equal to or less thana critical film thickness.
 14. The method of manufacturing thesemiconductor device according to claim 11, wherein the Ge concentrationof the first Si layer and the Ge concentration of the second Si layer isin a range from 20% to 40% in atomic %.
 15. The method of manufacturingthe semiconductor device according to claim 11, wherein each of thesource and the drain region includes B as p-type impurity, and theconcentration of B is in the range from 1×10¹⁹ cm⁻³ to 1×10²¹ cm⁻³. 16.A method of manufacturing a semiconductor device comprising: forming agate insulating film and a gate electrode over a Si substrate; forming arecess in the Si substrate at both sides of the gate electrode; forminga first Si layer including C in the recess; forming a interlayer overthe first Si layer; forming a second Si layer including C over theinterlayer; wherein the interlayer is composed of Si or Si including C,and a C concentration of the interlayer is less than a C concentrationof the first Si layer and a C concentration of the second Si layer. 17.The method of manufacturing the semiconductor device according to claim16, wherein the first Si layer is formed by epitaxial growth, theinterlayer is formed by epitaxial growth, and the second Si layer isformed by epitaxial growth.
 18. The method of manufacturing thesemiconductor device according to claim 16, wherein the thickness ofeach of the first Si layer, and the second Si layer is equal to or lessthan a critical film thickness.
 19. The method of manufacturing thesemiconductor device according to claim 16, wherein the C concentrationof the first Si layer and the C concentration of the second Si layer isin the range from 1% to 2% in atomic %.
 20. The method of manufacturingthe semiconductor device according to claim 16, wherein each of thesource and the drain region includes P or As as n-type impurity, and theconcentration of P or As is in the range from 1×10¹⁹ cm⁻³ to 1×10²¹cm⁻³.